The present invention relates to a data transfer apparatus and particularly to a technique for transferring data between apparatuses such as work stations and computers. More particularly, the present invention relates to a data transfer technique for latching a plurality of data input externally in synchronism with a clock input externally.
When data is transferred from one apparatus to another, there is considered a method in which data and clock are transmitted from a transmitting apparatus to a receiving apparatus and the data is latched in the receiving apparatus at the timing of the clock.
FIG. 10 schematically illustrates an apparatus for achieving the above method, and numeral 101 represents a transmitting apparatus, D(0) to D(n) represent data to be transferred, CK represents a clock to be transferred, L.sub.out (0) to L.sub.out (n) represent latch circuits for synchronizing the data to be transmitted with the clock, 102 represents a delay circuit for delaying the clock, T(0) to T(n) and T(CK) represent transmission lines such as wirings on a printed wiring board and cables for connecting apparatuses, 103 represents a receiving apparatus and L.sub.in (0) to L.sub.in (n) latch circuits for latching received data and which are of edge-triggered type.
FIG. 11 is a timing chart for illustrating operation of the apparatus of FIG. 10. Since there are differences in the propagation time of the data and clock in the circuits and the transmission lines in the transmitting and receiving apparatuses when the data and clock are transferred, the arrival timings of the data and clock to the receiving apparatus 103 are scattered between the period of time designated by (tskw.sub.-- prop). In order to latch the data in the receiving apparatus, it is necessary to design the timing in consideration of the scattering. More particularly, the clock is delayed by a time designated by tdly with respect to the data by the delay circuit 102 of the transmitting apparatus to be transmitted so that the rising edge of the received clock satisfies a set-up time (the data is required to be settled before a predetermined time of the clock and the predetermined time is called the set-up time tsu) and a hold time (the data is required to be held until after a predetermined time of the clock and the predetermined time is called the hold time th) of the latch within the valid area of the received data. Even if the design can be made to neglect the scattered delay time due to the delay circuit 102, the minimum repetition interval or cycle time of the data and clock at this time is a time designated by (2tskw.sub.-- prop+tsu+th). The general cycle time in the data transfer is of the order of about several nanoseconds to several tens of nanoseconds.
A well known example pertinent to the above prior art is described in "Latest SCSI Manual", pp. 160, issued by CQ on Feb. 1, 1989. For example, in order to compensate for differences in the propagation time between signals due to cables when data is transferred in the synchronous mode, it is necessary to satisfy the prescribed time for the data and clock (REQ or ACK) in the transmitting apparatus. The above example prescribes the minimum compensation time 55 ns from switching of the data to rising of the clock, the minimum compensation time 100 ns from rising of the clock to switching of the next data and the minimum cycle time 180 ns of the clock.
Further, JP-A-5-75594 discloses automatic adjustment of a phase between the data and the clock and a phase between parallel bits in the parallel data transfer.
A semiconductor device which does not concern the transfer of parallel data but controls a delay amount of a variable delay circuit by an external control signal to set a delay time for data and clock in order to take in the data externally in synchronism with an external clock is disclosed in JP-A-2-226316.
In the apparatus of FIG. 10, the minimum cycle time of the received data and clock is the time (2tskw.sub.-- prop+tsu+th) and the scattered propagation time of the signals from the transmitting apparatus to the receiving apparatus impedes the high-speed operation of data transfer.
Further, JP-A-5-75594 describes a bit phase synchronizing circuit on the side of the receiving apparatus in which the phase relation of the clock on the side of the receiving apparatus and the data for every parallel bit can be adjusted to latch the data without error, while the publication does not refer to any actual realization measures.
The semiconductor device disclosed in JP-A-2-226316 is a device for taking in one bit data, and requires new control measures in order to take in data composed of a plurality of bits.